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INTEGRATED CIRCUITS
DATA SHEET
SAA1575HL Global Positioning System (GPS) baseband processor
Product specification Supersedes data of 1999 May 17 File under Integrated Circuits, IC18 1999 Jun 04
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.8 7.8.1 7.8.2 7.8.3 7.8.4 7.9 7.9.1 7.9.2 7.9.3 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Overview The 80C51XA processor The GPS correlators Memory organization Data memory space Code memory space CPU peripheral features Timers/counters Watchdog timer UARTs RF IC programming port General purpose I/O The real-time clock The external bus Program memory chip select Data memory chip select Read strobe Write LOW byte strobe Write HIGH byte strobe Backup supplies and reset Supply domains Power-down design strategy System reset control Power saving modes Clock signals and oscillators System clock (XTAL1) RTC clock (XTAL3) Reference clock (RCLK) 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 LIMITING VALUES
SAA1575HL
THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS DEFAULT APPLICATION AND DEMONSTRATION BOARD PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
1 FEATURES
SAA1575HL
However, for compatibility with current automotive applications, the periphery is supplied from separate pins and can be operated between 3 and 5 V, as required. The function of the SAA1575HL is to read the 1 or 2-bit sampled IF bitstream from a front-end IC and, under control of firmware on an external ROM, calculate the full GPS solution. The results are communicated to a host in National Maritime Electronics Association (NMEA) format via a standard serial port. A second serial port can be used to provide differential GPS information to the processor for more advance applications. In addition, various other functions are integrated onto the IC such as a real-time GPS clock, a power-down/reset controller, timer/counters and a watchdog timer. To summarise, the SAA1575HL has the following functional units: * 16-bit 80C51XA microcontroller core * 2 kbytes words on-chip SRAM (16-bit words) * 8 GPS channel correlators * 2 UARTs * 8 general purpose I/O lines * 3 timer/counters * 1 real-time clock * 1 watchdog timer * 1 power-down/reset controller. The structure is based on a 16-bit microcontroller core operating on all other units as memory mapped peripherals and registers. A 16-bit data bus and a 19-bit address bus are extended to external pins so that external data and program memory can be accessed. On-chip decoder circuits eliminate the need for external glue logic for external memory access. Each of the 8 GPS channel correlators includes a carrier Numerically Controlled Oscillator (NCO), PN code generator, phase rotator and low-pass filter. They correlate the local PN sequence with the digitized input GPS signal and generate the filtered correlation result for the microcontroller. The firmware provided then generates a navigation solution and provides standard GPS data outputs to the user.
* Single-chip GPS baseband solution with built-in 16-bit microcontroller * All digital, 0.5 micron CMOS technology * Single power supply with full 3 V operation * Separate I/O power supply pins for operation with 3 or 5 V external devices * Up to 30 MHz system clock from on-chip crystal oscillator or external clock input * 2 kbytes words internal data memory for fast execution * External bus for up to 512 kbytes words data memory and 512 kbytes words program memory * Programmable external bus timing to match external memory speed * Chip selection outputs to reduce glue logic requirements * Reset controller for power-down detection and servicing * 8 GPS channel correlators driven by firmware for flexible GPS correlation algorithms * 1 second pulse output of GPS time * 2-bit digital IF GPS signal input synchronized to external sample clock * 2 fully duplex UARTs for communication with host system processor and other devices * Real-time clock with 32.768 kHz crystal and supply for low power timekeeping * Watchdog timer * Power-down modes under firmware control * 100-pin LQFP package * 50 mA supply current (typ.) when 8 GPS channels in track (approximate). 2 GENERAL DESCRIPTION
The SAA1575HL is an integrated circuit which implements a complete baseband function for Global Positioning System (GPS) receivers. It combines a 16-bit Philips 80C51XA microcontroller, 8 GPS channel correlators and related peripherals in a single IC. Users can implement a complete GPS receiver using only the SAA1575HL, the UAA1570HL front-end Philips IC (or similar), external memory and a few discrete components. The IC is aimed at low cost applications. A low power solution was also used where possible, although this was of secondary importance to cost. The core of the SAA1575HL operates at 3 V.
1999 Jun 04
3
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
The GPS firmware is located in off-chip program memory. It processes the GPS signals from up to 8 satellites and generates GPS information that can be output to the host processor through one of the two serial ports. Much of hardware configuration of the SAA1575HL can be controlled by the firmware and so details such as the external bus timing may change between firmware revisions. For the purpose of this document, the standard Philips firmware has been assumed (release HD00). 3 QUICK REFERENCE DATA SYMBOL VCC(core) VCC(P) VCC(R) VCC(B) ICC(core) ICC(R) ICC(B) PARAMETER core supply voltage peripheral supply voltage real-time clock core supply voltage backup peripheral supply voltage core supply current real-time clock core supply current backup peripheral supply current normal mode sleep mode fRTC = 32.768 kHz normal mode; dependent on load sleep mode ICC(P) fosc Tamb 4 peripheral supply current oscillator frequency ambient temperature normal mode sleep mode CONDITIONS MIN. 2.7 2.7 2.4 2.7 - - - - - - - 26 -40 TYP. 3.3 5.0 3.3 5.0 35 15 10 5 1 20 - 30 +25 MAX. 3.6 5.5 3.6 5.5 - - 30 - - - 1 32 +85 UNIT V V V V mA mA A mA A mA mA MHz C
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm VERSION SOT407-1
SAA1575HL
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
5 BLOCK DIAGRAM
SAA1575HL
handbook, full pagewidth
80C51XA PROCESSOR MODULE
83 UART 0 84 81 UART 1 82
TXD0 RXD0 TXD1 RXD1
STATIC RAM (2 kbytes WORDS)
80C51XA
CORE
TIMER 0, 1
XTAL1 XTAL2
14 15
SYSTEM CLOCK GENERATOR ADDRESS AND DATA
TIMER 2
WATCHDOG TIMER
D15 to D0 WRH WRL RD
48, 49, 53 to 59, 62 to 64, 67 to 70 45 46 47 EXTERNAL BUS INTERFACE
10, 11, 18 to 24, 27 to 29, 32 to 36, 39, 40 41 73
A19 to A1 PMCS DMCS
IF1
93
89 CORRELATORS CONTROL CONTROL REGISTERS 90 91 5 to 7, 87, 88, CHANNEL 0 94 to 96 CHANNEL 1 CHANNEL 2 REAL-TIME CLOCK CHANNEL 3 CHANNEL 4 74 CHANNEL 5 CHANNEL 6 CHANNEL 7 52 76 75
RFDAT RFCLK RFLE GPIO7 to GPIO0 XTAL3 XTAL4 PWRFAIL PWRDN RSTIME PWRM PWRB
IF2
92
RCLK
98
SCLK
1
T1S
2
SAA1575HL
RESET CONTROLLER
43 78 77
TEST1 TEST2
99 100 8, 9 97 72 80 12, 30, 66 16, 25, 37, 51, 61, 86 13, 17, 26, 31, 38, 50, 60, 65, 71, 79, 85 VSS 4 TP4 3 TP3 42 TP2 44 TP1
MHB460
n.c. VCC(R) VCC(B) VCC(core) VCC(P)
Fig.1 Block diagram.
1999 Jun 04
5
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
6 PINNING SYMBOL SCLK T1S PIN 1 2 I/O O O DESCRIPTION
SAA1575HL
Sample clock: sample clock generated internally by dividing down the RCLK (reference clock) input. This output is provided for use by the front-end IC. GPS time pulse: a 1 pulse per second output whose rising or falling edge (firmware controlled) is synchronized to GPS time when the receiver is tracking a GPS signal. The pulse length is approximately 1 ms. Test pin: tie HIGH Test pin: tie HIGH GPIO bit 5: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). GPIO bit 6: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). GPIO bit 7: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). Not connected: do not connect Not connected: do not connect External memory address bus bit 19: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 18: 19-bit address bus; used to address external RAM and program memory Main core power supply: 2.7 to 3.6 V only; main supply for the core in normal operation Ground: 0 V reference Crystal 1: input to the inverting amplifier; used in the system oscillator circuit and input to the internal clock generator circuits Crystal 2: output from the system oscillator amplifier Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation Ground: 0 V reference External memory address bus bit 17: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 16: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 15: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 14: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 13: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 12: 19-bit address bus; used to address external RAM and program memory
TP3 TP4 GPIO5
3 4 5
I I I/O
GPIO6
6
I/O
GPIO7
7
I/O
n.c. n.c. A19 A18 VCC(core) VSS XTAL1 XTAL2 VCC(P) VSS A17 A16 A15 A14 A13 A12
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
O O O O - - I O - - O O O O O O
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL A11 VCC(P) VSS A10 A9 A8 VCC(core) VSS A7 A6 A5 A4 A3 VCC(P) VSS A2 A1 PMCS TP2 RSTIME PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O O - - O O O - - O O O O O - - O O O I I DESCRIPTION
SAA1575HL
External memory address bus bit 11: 19-bit address bus; used to address external RAM and program memory Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation Ground: 0 V reference External memory address bus bit 10: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 9: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 8: 19-bit address bus; used to address external RAM and program memory Main core power supply: 2.7 to 3.6 V only; main supply for the core in normal operation Ground: 0 V reference External memory address bus bit 7: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 6: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 5: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 4: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 3: 19-bit address bus; used to address external RAM and program memory Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation Ground: 0 V reference External memory address bus bit 2: 19-bit address bus; used to address external RAM and program memory External memory address bus bit 1: 19-bit address bus; used to address external RAM and program memory External program memory select: external program memory read strobe Test pin: tie LOW Reset timer control: this controls the on-chip reset timer. If this is HIGH, reset will be de-asserted approximately 10 ms after both PWRDN and PWRFAIL go HIGH. If this is LOW, reset will be de-asserted approximately 10 s after both PWRDN and PWRFAIL go HIGH. Test pin: tie LOW Write MSB: write strobe for external data memory; asserted for both MSB and word write operations; input mode only used for test purposes Write LSB: write strobe for external data memory; asserted for both LSB and word write operations; input mode only used for test purposes External data read: read strobe for external data memory; input mode only used for test purposes
TP1 WRH WRL RD
44 45 46 47
I I/O I/O I/O
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL D15 D14 VSS VCC(P) PWRDN PIN 48 49 50 51 52 I/O I/O I/O - - I DESCRIPTION
SAA1575HL
External memory data bus: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 14: 16-bit data bus; used to connect to external RAM and program memory Ground: 0 V reference Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation Power-down indicator: a LOW on this pin asserts an XA interrupt intended for use as a power fail interrupt. Once reset is asserted, either by PWRFAIL or the firmware, it will remain asserted until a set time after this pin goes HIGH. External memory data bus bit 13: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 12: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 11: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 10: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 9: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 8: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 7: 16-bit data bus; used to connect to external RAM and program memory Ground: 0 V reference Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation External memory data bus bit 6: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 5: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 4: 16-bit data bus; used to connect to external RAM and program memory Ground: 0 V reference Main core power supply: 2.7 to 3.6 V only; main supply for the core in normal operation External memory data bus bit 3: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 2: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 1: 16-bit data bus; used to connect to external RAM and program memory External memory data bus bit 0: 16-bit data bus; used to connect to external RAM and program memory Ground: 0 V reference 8
D13 D12 D11 D10 D9 D8 D7 VSS VCC(P) D6 D5 D4 VSS VCC(core) D3 D2 D1 D0 VSS 1999 Jun 04
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71
I/O I/O I/O I/O I/O I/O I/O - - I/O I/O I/O - - I/O I/O I/O I/O -
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL VCC(R) PIN 72 I/O - DESCRIPTION
SAA1575HL
Backup core power supply: 2.4 to 3.6 V only. Separate from the core supply to allow a low capacity battery to be used to maintain the Real-Time Clock (RTC) function. This should be powered from the main supply during normal operation and switched to battery backup when the main supply fails. External data memory select: external RAM select pin, active LOW when the external data memory space is addressed. This output is driven from VCC(R) and VCC(B) supplies to ensure that the external RAM is not enabled during power-down. Power fail indicator: a LOW on this pin forces the embedded microcontroller into reset. Reset will not be de-asserted until a set time after both PWRDN and PWRFAIL go HIGH. For correct start-up, this pin should be LOW on power-up. Crystal 4: output from the RTC oscillator amplifier; this pin is only 3 V tolerant Crystal 3: input to inverting amplifier used in the RTC oscillator circuits (32.768 kHz); this pin is only 3 V tolerant Backup supply select: this output is intended to drive an external FET used to switch the battery backup supply(s). It is active LOW and is controlled directly by the PWRFAIL. Main supply select: this output is intended to drive an external FET used to switch the main supply(s). It is active LOW and is controlled directly by PWRFAIL. Ground: 0 V reference Backup I/O power supply: 2.4 to 5.5 V only. Supply for the RAM select, power fail and power switching I/O pads only allowing these functions to be powered when the main power supply fails. This should be powered from the main supply during normal operation and switched to battery backup when the main supply fails. Transmitter output 1: transmit channel for serial port 1 (UART1) of the embedded processor Receiver input 1: receive channel for serial port 1 (UART1) of the embedded processor. It is intended that this serial port is dedicated to differential GPS information (dependent on firmware). Transmitter output 0: transmit channel for serial port 0 (UART0) of the embedded processor. Receiver input 0: receive channel for serial port 0 (UART0) of the embedded processor. It is intended that this serial port is dedicated to the NMEA data stream (dependent on firmware). Ground: 0 V reference Main I/O power supply: 2.7 to 5.5 V operating range; main supply for the periphery in normal operation GPIO bit 4: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). GPIO bit 3: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). RFIC set-up data: serial data output used to set up the UAA1570HL front-end IC. RFIC set-up data: clock output for the serial data output used to set up the UAA1570HL front-end IC. The state of the RFDAT and RFLE lines is latched into the front-end IC on the rising edge. 9
DMCS
73
O
PWRFAIL
74
I
XTAL4 XTAL3 PWRB
75 76 77
O I O
PWRM VSS VCC(B)
78 79 80
O - -
TXD1 RXD1
81 82
O I
TXD0 RXD0
83 84
O I
VSS VCC(P) GPIO4
85 86 87
- - I/O
GPIO3
88
I/O
RFDAT RFCLK
89 90
O O
1999 Jun 04
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL RFLE IF2 IF1 GPIO2 PIN 91 92 93 94 I/O O I I I/O DESCRIPTION
SAA1575HL
RFIC setup latch: output used to latch the RFIC set-up into the active UAA1570HL control registers MSB IF input: MSB of the 2-bit GPS digital IF signal input. Clocked in on the rising edge of SCLK. If only a 1-bit IF input is available this input should be held HIGH. LSB IF input: LSB of the 2-bit GPS digital IF signal input. Clocked in on the rising edge of SCLK. GPIO bit 2: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). GPIO bit 1: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). GPIO bit 0: standard general purpose I/O mapped into the segment 15 of the address space. The top 4 bits can be used as the XA external timer control access pins (T0, T1, T2 and T2EX). Not connected: do not connect Reference clock: input from the TXCO reference. Not used internally. This is divided under firmware control to produce the sample clock, SCLK, used to gate the IF inputs. Test pin: connect to pin 100 Test pin: connect to pin 99
GPIO1
95
I/O
GPIO0
96
I/O
n.c. RCLK TEST1 TEST2
97 98 99 100
O I I O
1999 Jun 04
10
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
86 VCC(P) 85 VSS
80 VCC(B) 79 VSS
89 RFDAT
90 RFCLK
100 TEST2
78 PWRM
99 TEST1
96 GPIO0
95 GPIO1
94 GPIO2
88 GPIO3
87 GPIO4
77 PWRB
98 RCLK
84 RXD0
82 RXD1
91 RFLE
83 TXD0
81 TXD1
handbook, full pagewidth
76 XTAL3 75 XTAL4 74 PWRFAIL 73 DMCS 72 VCC(R) 71 VSS 70 D0 69 D1 68 D2 67 D3 66 VCC(core) 65 VSS 64 D4 63 D5 62 D6 61 VCC(P) 60 VSS 59 D7 58 D8 57 D9 56 D10 55 D11 54 D12 53 D13 52 PWRDN 51 VCC(P) VSS 50
97 n.c.
93 IF1
SCLK T1S TP3 TP4 GPIO7 GPIO6 GPIO5 n.c. n.c.
1 2 3 4 5 6 7 8 9
A19 10 A18 11 VCC(core) 12 VSS 13 XTAL1 14 XTAL2 15 VCC(P) 16 VSS 17 A17 18 A16 19 A15 20 A14 21 A13 22 A12 23 A11 24 VCC(P) 25 VSS 26 A10 27 A9 28 A8 29 VCC(core) 30 VSS 31 A7 32 A6 33 A5 34 A4 35 A3 36 VCC(P) 37 VSS 38 A2 39 A1 40 PMCS 41 TP2 42 RSTIME 43 TP1 44 WRH 45 WRL 46 RD 47 D15 48 D14 49
92 IF2
SAA1575HL
MHB461
Fig.2 Pin configuration.
1999 Jun 04
11
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7 7.1 FUNCTIONAL DESCRIPTION Overview
SAA1575HL
Both the RTC and the correlators are asynchronous to the system clock, with synchronization being achieved by firmware and interrupts. 7.2 The 80C51XA processor
The function of the SAA1575HL is to accept any IF data (1 or 2-bit) from a front-end RF IC (such as the UAA1570HL) and provide a serial NMEA compatible GPS position and time output. The IF input is sampled synchronously with the front-end reference clock, SCLK. Data is decoded from the IF input stream by one of eight parallel correlators which allow up to eight satellites to be tracked at one time. The acquisition, allocation and tracking of the satellites is performed under firmware control by the on-chip processor. In addition to the SAA1575HL and an appropriate front-end IC (such as the UAA1570HL), the only external components required to complete a functional GPS receiver are some RAM, the firmware ROM and some discrete devices to control the power supplies. The need for external glue logic is eliminated by various chip-select functions implemented on the SAA1575HL. The SAA1575HL also contains an optional independent Real-Time Clock (RTC) which requires a separate 32.768 kHz crystal. This can be set to GPS time by the processor and enables fast re-acquisition (a warm start) of satellites after power has been switched off. A separate supply pin is provided to allow the RTC to be powered while the rest of the IC is turned off. The block diagram of the SAA1575HL is shown in Fig.1. The IC consists of a processor core, its associated peripherals, some internal memory and a series of GPS correlators. The processor core is based on an embedded Philips 80C51XA (known as the XA). The XA peripherals (UARTs, timers, watchdog and general purpose I/Os) are termed special function registers and are memory mapped in parallel with an area of the data memory. They are connected to the core by dedicated data and address buses. The internal data memory is also connected to the core by a dedicated bus. The rest of the IC (the correlators, RTC and system control) is mapped into the external data memory space. The multiplexed data and address buses provided by the XA core are separated by an on-chip latch to provide the distinct 16-bit data bus and 19-bit address bus. These are made available externally for connection to external memory via the external bus interface. The correlators, RTC and system control blocks are memory mapped into the highest page of the 16 pages in the XA data structure.
The microcontroller core in the SAA1575HL is a Philips design called the XA (eXtended Architecture) which is an extended 80C51-like 16-bit microcontroller. This is largely compatible with the 8051 but with various improvements. The main features of the XA compared to the 8051 can be summarized as follows: * 16-bit versus 8-bit data processing * 20-bit versus 16-bit address bus * 3 clock instruction cycle versus 12 clock instruction cycle * 10 Mips versus 1 Mips * 20 CPU registers versus 1 accumulator * All 20 CPU registers in the XA can be used as the accumulator register in the 8051 * 16 x 16 multiplication in 12 clocks, 3216 division in 22 clocks * New type of instructions such as normalization, sign extension and trap * Multi-tasking support versus no multi-tasking support. 7.3 The GPS correlators
The correlator block forms the GPS specific hardware for correlating with the direct sequence spread spectrum GPS signals. The 8 identical correlators share the 2-bit IF input and the sample clock of the Analog-to-Digital Converter (ADC) of the front-end. The input signal is the 50 bits/s GPS data spread by the 1.023 Mbits/s PN code and modulated by the residual carrier. The residual carrier frequency is composed of the Doppler frequency and the receiver local oscillator frequency offset. To recover the GPS data and find the accurate timing of the received data for GPS navigation from the low-level (as low as -130 dBm) GPS signal, the residual carrier frequency and phase have to be found by a Phase-Locked Loop (PLL) with minimum tracking phase error. The starting position of the PN code in the received signal is found by correlation within a Delay-Locked Loop (DLL). The channel correlator includes a local numerically controlled oscillator and a programmable local PN code generator with the phase rotation and correlation circuit.
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.4 Memory organization
SAA1575HL
The specifications of this external memory are firmware dependent. The figures given in this document are for the standard Philips firmware. With other revisions of firmware the timings could differ by integer numbers of XTAL1 clock cycles. In the SAA1575HL, all of the data read and write cycles are preceded by an internal Arithmetic and Logic Elements (ALEs) cycle (as in any standard 80C51 system). The multiplexed address/data bus and the ALE signal are not available externally. However, for clarity, these are illustrated in Figs 3 to 6.
The memory space in the SAA1575HL is configured in a Harvard architecture which means that the code and data memory are organized in separate address spaces. This section describes the SAA1575HL memory requirements. 7.4.1 DATA MEMORY SPACE
The SAA1575HL contains 2 kbytes words of internal data memory. For correct firmware operation, a further 32 kbytes words of external data memory is needed with a maximum access time of 100 ns.
handbook, full pagewidth
XTAL1
ALE internal signals address/ data address external data
address bus
address
RD
DMCS
MHB462
The timing is configurable under firmware control.
Fig.3 Example of external data read (standard firmware).
1999 Jun 04
13
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
XTAL1
ALE internal signals address/ data address external data
address bus
address
WRH/WRL
DMCS
MHB463
The timing is configurable under firmware control.
Fig.4 Example of external data write (standard firmware).
7.4.2
CODE MEMORY SPACE
The SAA1575HL has no internal code memory. The GPS solution firmware resides in external memory. With the standard Philips firmware, a ROM with a maximum access time of 100 ns is required. The classic operation of a multiplexed address/data bus involves an address being set-up for every bus cycle. The internal ALE signal is used to latch the address prior to the cycle on which the data is set-up. An example of the resulting timing is illustrated in Fig.5. The SAA1575HL does not require an internal ALE cycle for each code fetch. The lowest 3 address lines are not multiplexed with the data lines and so these can be used to incrementally read code locations.
The XA core can therefore issue up to 8 word reads through sequential code memory for each ALE cycle. This is termed a burst code read. An example of the resulting timing is illustrated in Fig.6. Any type of branch or jump in the program may require a code fetch in a non-sequential manner and a new ALE cycle will be needed. This may occur at any stage in a code read. Thus the length of the read strobe in a burst read is not necessarily an integer multiple of the individual code read length.
1999 Jun 04
14
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
XTAL1
ALE internal signals address/ data address
address bus
address
PMCS
DATA BUS
data input
MHB464
The timing is configurable under firmware control.
Fig.5 Example of code read with ALE (standard firmware).
handbook, full pagewidth
XTAL1
ALE internal signals address/ data address bus address 1 address 2
address 1
address 2
PMCS
DATA BUS
code word 1
code word 2
MHB465
The timing is configurable under firmware control.
Fig.6 Example of burst mode code read (standard firmware).
1999 Jun 04
15
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.5 CPU peripheral features
SAA1575HL
With the standard Philips firmware, both UARTs are configured to be in Mode 1: variable rate 8-bit operation. Ten bits are transmitted (via TXDn) or received (via RXDn): a START bit, 8 data bits (LSB first), and a STOP bit. In general, the UART clocks (which are 16 times the baud rate) are determined by the Timer 1 or Timer 2 overflow rate. With the standard Philips firmware, Timer 1 is used to generate the baud rate for UART0 and Timer 2 is used to generate the baud rate for UART1. The baud rate is set to be 4800 bits/s for both UARTs. 7.5.4 RF IC PROGRAMMING PORT
The SAA1575HL contains the hardware for 3 timers, 2 UARTs, a watchdog timer, a 3-bit RF IC programming link and an 8-bit general purpose I/O port. 7.5.1 TIMERS/COUNTERS
The SAA1575HL has 2 standard 16-bit timer/counters and a third 16-bit up/down timer/counter. These timer/event counters can perform the following functions: * Measure time intervals and pulse duration * Count external interrupts * Generate interrupt requests * Generate Pulse Width Modulation (PWM) or timed output waveforms. The timers are used by the standard Philips firmware to generate the baud rates for the UART serial ports. The additional features are not used in the standard Philips firmware but are available for use in custom firmware revisions. All of the timers are configured in the 16-bit auto-reload mode of operation. Timer 1 is used to generate the baud rate for UART0 and Timer 2 is used to generate the baud rate for UART1. In the standard Philips firmware, Timer 0 is not used. 7.5.2 WATCHDOG TIMER
The SAA1575HL is capable of programming the UAA1570HL via a standard 3-wire serial link. This consists of a clock line (SCLK), data line (D15 to D0) and a latch enable (RFLE). Data is clocked into a holding register in the UAA1570HL serially on each rising edge of the output RFCLK. Once the complete serial packet has been clocked into the RF IC, the latch enable output, RFLE, is asserted which copies the new word from the holding register in the RF IC into the control registers. Proper timing of the clock, data and latch outputs is ensured by firmware. An example sequence is illustrated in Fig.7. The signals shown would result in the value 1001 being loaded into the last 4 bits of the RF IC serial register. Each loading operation of the RF IC reloads the complete RF control register. With the standard Philips firmware, a 20-bit long word 0X5E320 is transmitted in this manner on start-up or re-initialization. This gives full compatibility with the Philips UAA1570HL front-end IC. See the "UAA1570HL" for more details about the configuration options of the front-end IC.
The watchdog timer protects the system from incorrect code execution by causing a processor reset if the watchdog timer underflows as a result of a failure of the firmware to feed the timer prior to it reaching its terminal count. In the standard Philips firmware, the watchdog is enabled with a time-out period of 130 ms (at a clock frequency of 30 MHz). 7.5.3 UARTS
The SAA1575HL contains 2 UART ports, compatible with the enhanced UART modes 1 to 3 on the 8xC51FB (mode 0 operations not supported). With the exception of the removal of the mode 0 operation, the UARTs in the SAA1575HL are identical to those in the XA-G3 product. Each UART rate is determined by either a fixed division of the oscillator (in UART mode 2) or by one of the timer overflow rates (in UART modes 1 and 3).
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
RFDAT
RFCLK
RFLE
holding
XXXX
XXX1
XX10
X100
1001
control
XXXX
1001
MHB466
X = don't care.
Fig.7 Example timing for UAA1570HL programming.
7.5.5
GENERAL PURPOSE I/O
The SAA1575HL possesses an 8-bit general purpose I/O register and 8 associated I/Os (see Fig.8). With the standard Philips firmware, all 8 of these pins are configured as outputs. With the standard Philips firmware, only pin GPIO0 is used. This is switched on at the end of the firmware initialization sequence and remains on subsequently.
handbook, full pagewidth
VCC(P) 10 A pull-up FET Q IOn
WRITE ENABLE
CFGn
DATA BUS
EN D
GPIOn pin
CLK
READ ENABLE
MHB467
Fig.8 GPIO pin drive circuits.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.6 The real-time clock
SAA1575HL
The SAA1575HL uses a digital under-sampling system to ensure that ground bounce does not cause RTC timekeeping errors. This places a restriction on the ratio of XTAL1 and XTAL3 frequencies for which the RTC will operate correctly. This has been optimistic for the case fXTAL1 = 30 MHz, fXTAL3 = 32 kHz and, assuming that the RTC crystal frequency will always be 32 kHz, will operate correctly for the entire specified range of system frequencies.
The Real-Time Clock (RTC) is a functional unit used to generate time information. Its purpose is to supply approximate GPS time to the system firmware for the initial acquisition of satellites (a warm start). The power supply for the RTC is separate from the rest of the IC, allowing a low capacity battery to be used to maintain the low power RTC function. The timebase for the RTC should be provided by a dedicated 32.768 kHz crystal which can be omitted if the RTC is not required. This is divided down by a fixed divider to provide the 1 Hz timebase used for the rest of the RTC block. A digital sampling circuit is also included to prevent digital noise due to the on-chip processor causing incorrect timekeeping.
handbook, full pagewidth
off-chip XTAL3 C
XTAL (optional)
OSCILLATOR
32 kHz
SAMPLER
32 kHz
PRE-SCALER
1 Hz
REAL-TIME CLOCK COUNTERS
C
XTAL4
system clock
MHB468
Fig.9 Real-time clock circuit.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.7 The external bus
SAA1575HL
However, since internally there is still the need to latch the address from a common address/data bus, signals on the data bus will be seen to change during the address set-up cycles. The lower 3 external address lines are driven directly by the XA core and are not latched. This allows `burst' code reads to be performed in which adjacent code locations are accessed without the need for an address latch cycle. Signals similar to those used by a standard 80C51 or XA system are used to control the external bus activity.
The off-chip memories and the on-chip registers are on the same address and data bus. The routing of the data and address signals between the on-chip registers and the off-chip memories is controlled by a block known as the external bus interface. In addition, certain chip enable signals are decoded within the block to reduce the amount of external glue logic required in the complete system. The address latch, normally required on 80C51 systems, is implemented within the SAA1575HL. Therefore, no ALE signal is seen outside the IC and address and data lines are brought out on separate pins.
handbook, full pagewidth
to MMRS A1 to A8 D15 to D0 ENABLE
16 ALE A4 to A19 D15 to D0 ADDRESS LATCH XA LE
ADDRESS DECODER 16
DMCS
A4 to A19
16 A3 to A1 WRH, WRL, RD PMCS
MHB469
D15 to D0 A3 to A1 WRH, WRL, RD PMCS
3 3
Fig.10 SAA1575HL internal address and data routing.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.7.1 PROGRAM MEMORY CHIP SELECT 7.8 Backup supplies and reset
SAA1575HL
This signal (PMCS) is an active LOW strobe used to enable the output of the external code memory. It remains HIGH when a read code is not in progress. 7.7.2 DATA MEMORY CHIP SELECT
This signal (DMCS) is an active LOW strobe used to enable the external data memory. The SAA1575HL hardware supports two distinct modes of operation of this signal (selected in firmware) designed for optimum power or optimum speed. The standard Philips firmware is configured for optimum power. DMCS is taken LOW during an external data read or write operation to segments 0 to 14 of the memory map. To prevent the corruption of external data memory, the DMCS pin is driven on the backup supply voltage and will be held HIGH once the PWRFAIL signal has been asserted LOW. With the standard Philips firmware, the DMCS signal is gated by the external access read and write strobes. This should significantly reduce the power consumption of the external RAM but may require the use of a slightly faster external memory (depending on clock speed and details of the external memory used). 7.7.3 READ STROBE
The SAA1575HL is designed to operate correctly in situations when the main power supply fails. In addition to the main core and peripheral power supplies, separate pins are provided for backup core and peripheral supplies which enable critical (and low-power) functions to be maintained during the loss of main power. There is also an on-chip reset timer which will aid the design of a full power-down strategy. 7.8.1 SUPPLY DOMAINS
To allow for the use of inexpensive 5 V external components, the periphery of the SAA1575HL can be powered with a higher voltage than the core. Therefore there is a distinction between the core and peripheral power supplies. In addition, there is the need to maintain certain functionality on a low-power supply in the event of main power failure. Therefore there are 2 additional supplies required for so-called backup operation. Thus there are four distinct power supply domains, two for the core supplies and two for the peripheral supplies. Table 1 Supply domains PURPOSE provides power for all core circuits, excluding those mentioned below
SUPPLY DESCRIPTION VCC(core) main core supply (3 V)
This signal (RD) is an active LOW strobe used to indicate that the XA is expecting data from the external bus. 7.7.4 WRITE LOW BYTE STROBE
VCC(P)
main peripheral provides power for all pins, supply excluding those mentioned (3 to 5 V) below RTC core supply (2.4 to 3 V) powers the real-time clock, the 32 kHz oscillator and the 32 kHz de-bounce circuit; it also produces the signals for DMCS, PWRM and PWRB provides power for the following pins: DMCS, PWRM, PWRB and PWRFAIL
This signal (WRL) is an active LOW strobe used to indicate that the XA is performing an external write. This strobe only applies to the lower data byte of the 16-bit data word, allowing byte writes to be performed from the 16-bit data. This strobe will also be taken LOW for word write operations. 7.7.5 WRITE HIGH BYTE STROBE
VCC(R)
VCC(B)
This signal (WRH) is an active LOW strobe used to indicate that the XA is performing an external write. This strobe only applies to the higher data byte of the 16-bit data word, allowing byte writes to be performed from the 16-bit data. This strobe will also be taken LOW for word write operations.
backup peripheral supply (2.4 to 5 V)
In normal operation, the backup core and pad supplies should be provided from the main power supply rather than a low-capacity battery since the power drawn on the backup supplies while the processor is operating may be significant. Two output pins, PWRM and PWRB are provided to control this switching.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
The power consumption of the SAA1575HL in the power-down mode is minimal since no outputs are changing. The only active circuit in power-down is the real-time clock. Isolation between the power domains is controlled by the PWRFAIL input pin. This must be driven LOW in a power-failure situation to ensure that the backup domains are isolated from the main supply domains. If this is not done, it is possible that the registers contained in the backup supply domain will be corrupted as the main supply is cycled. It is also possible that under these circumstances a high backup supply current will be drawn (depending on details of the external supply circuitry). 7.8.2 POWER-DOWN DESIGN STRATEGY
SAA1575HL
The power-down and power-fail operations of the SAA1575HL are controlled by two inputs, PWRDN and PWRFAIL, which are assumed to be connected to external voltage comparators. The use of external comparators allows the voltage thresholds to be set by the system designer. It also allows a certain amount of flexibility as to which supplies are monitored for power failure.
7.8.2.1
Power-down control signals
The power-down control signal pins (see Table 2) are either inputs or outputs associated with the SAA1575HL power control. The descriptions are for the intended use of the control signals in a normal application. For a correct reset to occur, it is important that PWRFAIL should be held LOW as long as minimum voltages have been established on all four of the power supply domains. If this is not done various serious consequences may occur, including main oscillator failure, a high supply current state, a processor crash or RTC register corruption.
In power-down operation the main supplies are assumed to have failed. The backup core and pad supplies should be switched to backup power. The detection of the power failure and the power supply switching is the responsibility of the user. However, the SAA1575HL does provide several functions to aid this task. Table 2 Power-down control signals
SIGNAL PWRDN
FUNCTION Power-down indicator: this should be driven LOW by an external comparator to indicate impending power failure. Internally it sends an interrupt to the processor used to initiate a power-fail routine. At the end of this routine the standard firmware forces the processor into reset. This also inhibits the external RAM chip select. Reset is only de-asserted a set time after both PWRDN and PWRFAIL go HIGH, controlled by the RSTIME input. Power fail indicator: this should be driven LOW by an external comparator to indicate immediate power failure. Internally it forces immediate reset of the processor, isolation of the RTC and inhibition of the external RAM chip select. It also controls the power switch outputs PWRB and PWRM. Reset is only de-asserted a set time after both go HIGH, controlled by the RSTIME input. Reset timer control: this sets the time delay between de-assertion of both PWRDN and PWRFAIL and the de-assertion of the processor reset. If HIGH, the delay is approximately 10 ms. If LOW the delay is approximately 10 s. External RAM chip select: this is driven via the backup supplied core and pads. In power-down this is isolated from the rest of the IC and the output held HIGH to prevent corruption of the external RAM. Main power supply control: in normal operation this is held LOW. This can be used to switch the main supplies to all of the supply input pins. In normal operation the backup pad supply pin should be driven by the main supply and the backup core supply pins should be driven by the main core supply. When the IC goes into power-down mode this output goes HIGH. In power-down the backup supply pins should be driven by their appropriate supplies. Backup power supply control: this is the inverse of PWRM
PWRFAIL
RSTIME
DMCS PWRM
PWRB
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.8.2.2 Example of strategy for slow supplies
SAA1575HL
At the end of the interrupt routine, the firmware places the SAA1575HL into reset. As VCC(P) continues to fall, the second threshold is reached and is taken LOW. This toggles the power controls, both PWRM and PWRB, and will force a reset if it has not already occurred. On power-up, the power controls both PWRM and PWRB will be switched once the second threshold voltage is reached. As the supply voltage rises further, the first voltage threshold will be reached at which time both PWRDN and PWRFAIL will be HIGH. This starts the reset counter and the SAA1575HL will remain in reset until a set time after this, depending on the state of the input pin RSTIME.
The ultimate use of the power control signals is up to the user. However, two possibilities are presented as design examples. The first example will operate correctly in circuits where the rise times of the power supplies is slow compared to any delay between the supplies to the peripheral and core power domains. In this example, both the PWRDN and PWRFAIL logic inputs to the SAA1575HL are derived by comparing the VCC(P) supply voltage against known references. In general, since it is a lower voltage, the VCC(core) supply may hold and reach it's nominal voltage quicker than the VCC(P) supply. As VCC(P) falls, the first threshold is reached and PWRDN is taken LOW. This triggers an interrupt in the firmware which is used to perform any required housekeeping. It is assumed that there is time for this to be completed before complete supply failure.
handbook, full pagewidth
Vt1
Vt2
VCC(P)
VCC(core)
PWRDN
PWRFAIL
PWRB
PWRM
delay while XA in interrupt routine
reset timer delay set by RSTIME
MHB470
Fig.11 Example of power-down strategy with slow supplies.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.8.2.3 Example of strategy for fast supplies
SAA1575HL
However, if the fall times on the supplies is fast, it is likely that the PWRFAIL input will go LOW before the interrupt routine has been completed. This would force the SAA1575HL into immediate reset. At this time both PWRM and PWRB toggle to switch backup supply sources. On power-up, the VCC(P) supply rises quickly. However, since this only controls an interrupt flag and the SAA1575HL is still held in reset by PWRFAIL, this has no effect. Only once the VCC(core) supply rises will PWRFAIL be de-asserted. This can only occur once the VCC(core) voltage has reached the set threshold, and so there is no risk of the IC `missing' the reset pulse. The SAA1575HL will come out of reset a set time after this, depending on the state of the input pin RSTIME.
The second example will operate correctly in circuits where the delay between the supplies to the peripheral and core power domains is significant compared to the rise times of the power supplies. This may occur in cases where the core supply is a regulated (delayed) version of the peripheral supply. If the previous strategy were used in this situation, it would be possible for the SAA1575HL to miss the PWRFAIL LOW state at power-up, resulting in the IC not being given a correct reset. In this example, the PWRDN logic input is derived as before by comparing the VCC(P) supply voltage against a known reference voltage. But in this instance the PWRFAIL logic input is derived by comparing the VCC(core) core supply against a threshold voltage. As VCC(P) falls, the first threshold level is reached and PWRDN is taken LOW. This triggers an interrupt in the firmware which is used to perform any required housekeeping. At the end of the interrupt routine, the firmware places the SAA1575HL into reset.
handbook, full pagewidth
Vt1
VCC(P) Vt3 VCC(core)
PWRDN
PWRFAIL
PWRB
PWRM
delay while XA in interrupt routine
reset timer delay set by RSTIME
MHB471
Fig.12 Example of power-down strategy with fast supplies.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.8.3 SYSTEM RESET CONTROL
SAA1575HL
7.8.3.2 Overall reset operation
The SAA1575HL contains an internal timer and control logic to perform various system reset tasks. Control of this logic is by three external pins, PWRDN, PWRFAIL, and RSTIME. This allows the system designer to set the voltage thresholds at which the system goes into and comes out of reset.
The assertion of the reset signal (by means already described) will cause the following to occur: * Internal XA processor reset * Internal registers reset * Data bus pins set to be inputs * Read and write strobes de-asserted * GPIO pins set to be inputs * On-chip XTAL1 oscillator enabled.
7.8.3.1
The reset timer
The heart of the reset system is a 20-bit counter with asynchronous reset, clocked from the XTAL1 system clock. The reset counter is asynchronously reset if the PWRFAIL pin is LOW. Once reset, the counter will only be enabled once both PWRFAIL and PWRDN go HIGH. This prevents the SAA1575HL from leaving the reset state until both power detect inputs have flagged the power system as healthy. The internal reset signal is generated by decoding the reset counter. The decode value, and hence the time delay, is controlled by the reset time control pin, RSTIME. Table 3 Reset time control NUMBER OF CYCLES BEFORE RESET DE-ASSERTED 294 912 288 TIME DELAY (fXTAL1 = 30 MHz) 9.8 ms 9.6 s
7.8.3.3
CPU reset operation
Assuming that the correct external PWRFAIL sequence is generated on power-up, the internal XA will receive the correct reset signal from the on-chip reset block. If the proper PWRFAIL is not performed, the operation of the on-chip reset block cannot be guaranteed and the XA may fail wholly or in part. The embedded XA requires a minimum length of reset to complete the various tasks. This minimum length is guaranteed by the on-chip reset block. The only restriction on the length of the pulse is that is should be long enough to be asynchronously detected by the SAA1575HL (typically 10 ns). The embedded CPU can also be reset by the watchdog timer (this may be disabled on some custom firmware revisions). 7.8.4 POWER SAVING MODES
RSTIME INPUT 1 0
The internal reset is de-asserted a given number of XTAL1 clock cycles after PWRFAIL and PWRDOWN go HIGH. It is suggested that for most applications RSTIME should be held HIGH, giving a reset time of approximately 10 ms. This would be needed to allow the on-chip oscillator to stabilize after power-up. The shorter reset time can be used for applications using an external XTAL1 clock signal which does not need a long stabilization period. It is important that PWRFAIL should be LOW during power-up of the IC to give the correct reset.
The SAA1575HL supports two power saving modes; Idle mode and sleep mode. Both modes are selected by firmware (or message over the serial link if included in the firmware). In addition, the input to any of the correlators can be inhibited individually (by firmware) which will reduce the power consumed by the block to only the clock tree dissipation.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.8.4.1 Sleep mode
7.9
SAA1575HL
Clock signals and oscillators
The sleep mode is intended to overlay the function of the standard 80C51XA Idle mode. Sleep is initiated by a firmware or external serial link command. This initiates a firmware routine which performs the following: 1. Send serial command to power-down RF IC (UAA1570HL) 2. Inhibit RCLK, IF2 and IF1 inputs to SAA1575HL 3. Enter standard 80C51XA Idle state. In sleep mode the RCLK and IF inputs are prevented from entering the IC. This capability is included to cover the situation in which the SAA1575HL is used with a front-end which does not respond to the power-down command in a similar way to the UAA1570HL. Sleep mode can be exited by any active hardware interrupt, for example a UART interrupt. The sleep mode has no effect on the operation of the RTC.
The SAA1575HL requires 3 clock signals for full operation: * XTAL1: Processor (system) clock * XTAL3: Real-time clock crystal frequency (optional) * RCLK: GPS reference clock. Two of these clocks, XTAL1 and XTAL3, can be generated by on-chip oscillator circuits. The third, RCLK, must be supplied from an external source; in most applications a temperature compensated oscillator module. 7.9.1 SYSTEM CLOCK (XTAL1)
7.8.4.2
Idle mode
The Idle mode is initiated by a firmware or external serial link command. This is a direct use of the standard 80C51XA Idle mode. The interrupt signals from the active peripherals such as UARTs, timers, host interface and external interrupts will cause the CPU to resume execution from the point at which it was halted. In the Idle mode, all of the output pins retain their logic states from their `pre-idle' position. No other action is taken on entering Idle mode. In particular, the correlators will remain active since RCLK, IF1 and IF2 will not be prevented from entering the IC.
The SAA1575HL requires a system clock for the on-chip processor and related peripheral blocks. This can be provided from an external clock source via the XTAL1 input pin or by using the on-chip oscillator circuit with an external resonating element connected between the XTAL1 and XTAL2 pins. In most circumstances this would be an external crystal accompanied by two capacitors connected to ground, a series resistor (to optimize power consumption) and a shunt resistor to ensure start-up under all conditions. Optimum values of C, RP and RS will depend on the crystal used. However, typical values would be C = 20 pF, RP = 1 M and RS = 200 . The hardware places a restriction on the range of frequencies for which correct operation will occur; 26 MHz < fXTAL1 < 32 MHz. However, the restriction on operating frequency imposed by the firmware is tighter than this. The standard Philips firmware has been written on the assumption of a 30 MHz system clock frequency.
handbook, halfpage off-chip
on-chip XTAL1
C XTAL RP (optional) OSCILLATOR system clock
C
RS (optional)
XTAL2
MHB472
Fig.13 System clock oscillator circuit.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
7.9.2 RTC CLOCK (XTAL3) 7.9.3 REFERENCE CLOCK (RCLK)
SAA1575HL
If the on-chip real-time clock is required (as with the standard Philips firmware), a low frequency clock signal is required to run the clock. The SAA1575HL is designed so that a standard 32.768 kHz watch crystal can be used for this purpose. Since this is much slower than the system clock, a much lower power is required to run just the real-time clock, allowing it to be powered from a low-capacity battery when the main power supply fails. As with the system clock, there is an on-chip oscillator so that only a few passive external components are required. These would be an external crystal accompanied by two capacitors connected to ground, a series resistor (optional) and a shunt resistor to ensure start-up under all conditions. Optimum values of C and RP will depend on the crystal used. However, typical values would be C = 22 pF and RP = 1 M.
The reference clock input, RCLK, is used as the source for the sampling of the IF input signal. A divided-down version of RCLK is output on the sample clock pin, SCLK, for use by the front-end IC. The division ratio of RCLK/SCLK is programmable in firmware. In the standard Philips firmware this ratio is set to 3.
handbook, halfpage off-chip
on-chip XTAL3
C XTAL RP (optional) OSCILLATOR RTC clock
C
XTAL4
MHB473
Fig.14 RTC clock oscillator circuit.
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC(core) VCC(R) VCC(P) VCC(B) VCC Ptot Tstg Tj Tamb Ves PARAMETER core supply voltage RTC core supply voltage peripheral DC supply voltage backup peripheral DC supply voltage absolute voltage differences between two VCC pins total power dissipation storage temperature junction temperature ambient temperature electrostatic handling VCC(core) = VCC(R) = 3.3 V; VCC(P) = VCC(B) = 5.0 V note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1.5 k. 2. Machine model: C = 200 pF; L = 0.75 H; R = 0 . 9 THERMAL CHARACTERISTICS PARAMETER thermal resistance from junction to ambient CONDITIONS in free air CONDITIONS
SAA1575HL
MIN. -0.5 -0.5 -0.5 -0.5 - - -65 - -40 2000 200
MAX. +3.6 +3.6 +5.5 +5.5 550 500 +150 150 +85 - -
UNIT V V V V mV mW C C C V V
SYMBOL Rth(j-a)
VALUE 45
UNIT K/W
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
10 DC CHARACTERISTICS VCC(P) = VCC(B) = 5 V; VCC(core) = VCC(R) = 3 V; Tamb = 20 C; fosc = 30 MHz; standard Philips firmware (release HD00); note 1; unless otherwise specified. SYMBOL Supplies VCC(core) VCC(P) VCC(R) VCC(B) ICC(core) core supply voltage peripheral supply voltage RTC core supply voltage backup peripheral supply voltage core supply current normal mode idle mode sleep mode ICC(P) peripheral supply current normal mode; note 2 idle mode sleep mode ICC(R) RTC core supply current normal mode; note 3 idle mode; note 3 sleep mode; note 3 ICC(B) backup peripheral supply current normal mode; note 2 idle mode sleep mode 2.7 2.7 2.4 2.7 - - - - - - - - - - - - - 3.5 - 2.4 - - CL = 5 pF CL = 25 pF VOL VOH Idrive(max) CL(max) td(t) LOW-level output voltage HIGH-level output voltage maximum drive current maximum load capacitance transition delay CL = 10 pF CL = 50 pF IOL = 4.0 mA IOH = 1.0 mA - - - 2.4 - - - - 3.3 5.0 3.3 5.0 35 15 - 20 - - 10 10 10 5 1 1 - - - - - - 7.4 8.8 - - - - 6.8 8.1 3.6 5.5 3.6 5.5 - - 10 - 1 1 30 30 30 - - - V V V V mA mA A mA mA mA A A A mA A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Inputs: pins PWRFAIL, PWRDN, RSTIME, RXD1, RXD0, IF2, IF1, RCLK, TEST1, TP1, TP2, TP3 and TP4 VIL VIH VOL VOH Idrive(max) CL(max) td(t) LOW-level input voltage HIGH-level input voltage 1.5 - V V
Outputs (LOW drive current): pins PWRB, PWRM, T1S, RFCLK, RFDAT, RFLE and TEST2 LOW-level output voltage HIGH-level output voltage maximum drive current maximum load capacitance transition delay IOL = 2.0 mA IOH = 0.5 mA 0.4 - 2 50 - - V V mA pF ns ns
Outputs (HIGH drive current): pins A19 to A1, DMCS, PMCS, TXD0, TXD1 and SCLK 0.4 - 4 100 - - V V mA pF ns ns
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL PARAMETER CONDITIONS - 3.5 IOL = 4.0 mA IOH = 1.0 mA - 2.4 - - CL = 10 pF CL = 50 pF I/O (pull-up): pins D15 to D0 and GPIO7 to GPIO0 VIL VIH VOL VOH Idrive(max) CL(max) td(t) Ipu Notes 1. XTAL1, XTAL2, XTAL3 and XTAL4 are not specified with respect to levels. 2. Depends on all the external circuit driven by outputs. 3. Specified at RTC clock frequency of 32.768 kHz. LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage maximum drive current maximum load capacitance transition delay pull-up current CL = 10 pF CL = 50 pF IOL = 4.0 mA IOH = 1.0 mA - 3.5 - 2.4 - - - - - - - - - - - 8.9 11.0 10 - - MIN. - - - - - - 7.0 8.7
SAA1575HL
TYP.
MAX.
UNIT
I/O: pins WRL, WRH and RD VIL VIH VOL VOH Idrive(max) CL(max) td(t) LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage maximum drive current maximum load capacitance transition delay 1.5 - 0.4 - 4 100 - - V V V V mA pF ns ns
1.5 - 0.4 - 4 100 - - -
V V V V mA pF ns ns A
1999 Jun 04
29
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
11 AC CHARACTERISTICS VCC(P) = VCC(B) = 5 V; VCC(core) = VCC(R) = 3 V; Tamb = 20 C; fosc = 30 MHz; standard Philips firmware (release HD00); unless otherwise specified. SYMBOL External clock fosc Tclk tCLKH tCLKL tr(clk) tf(clk) fclk(ref) tAVAU tAVPL tW(PMCS) tPLIV th(I) tAVIV tsu(I) tPXIZ th tAVAU tAVIV tIVAU tAUIU tAVAU tRLEL tW(DMCS) tRHEH tAVRL tW(RD) tAVDV tRLDV tsu(D) th(D) tRHDZ oscillator frequency clock period and CPU timing cycle clock HIGH time clock LOW time clock rise time clock fall time reference clock frequency 26 - 40 to 60% duty cycle - 40 to 60% duty cycle - - - - 30 33.3 6.7 6.7 5 5 14.4 32 - - - - - 35 - - - 85.0 - 151.7 - 36.0 - - 118.3 - - - 4.0 - 6.0 - - 151.7 85.0 - - 36.0 MHz ns ns ns ns ns MHz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
External program memory read (non-burst code read); see Fig.16 address valid time period address valid to PMCS asserted PMCS pulse width PMCS LOW to instruction valid instruction hold time after PMCS de-asserted address valid to instruction valid (access time) instruction set-up time before PMCS de-asserted bus 3-state after PMCS de-asserted hold time of a (3 : 1) after PMCS de-asserted 163.7 62.7 97.0 - 0.0 - 14.0 - 0.0 165.7 65.7 98.0 82.0 - 148.7 16.0 30.0 1.0 ns ns ns ns ns ns ns ns ns
External program memory read (burst code read); see Figs 16 and 17 address valid time period address valid to instruction valid (access time) instruction valid to address undefined address valid to instruction undefined 131.3 - 15.0 0.0 132.3 115.3 17.0 - ns ns ns ns
External data memory read; see Fig.18 address valid time period RD asserted to DMCS asserted DMCS pulse width RD de-asserted to DMCS de-asserted address valid to RD asserted RD pulse width address valid to data valid (access time) RD asserted to data valid data set-up time before RD de-asserted data hold time after RD de-asserted bus 3-state after RD de-asserted note 1 163.7 - 97.0 - 64.7 98.0 - - 15.0 0.0 - 164.7 2.0 98.0 2.0 65.7 - 148.7 82.0 16.0 - 30.0 ns ns ns ns ns ns ns ns ns ns ns
1999 Jun 04
30
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SYMBOL PARAMETER CONDITIONS MIN. - 2.0 - 2.0 - 65.7 - -4.0 - 1.0
SAA1575HL
TYP.
MAX. - 4.0 - 4.0 - - - - - -
UNIT
External data memory write; see Fig.19 tAVAU tWLDL tW(DMCS) tWHDH tAVWL tWLWH tAVQV tQVWL tWHAU th(D) address valid time WRH and WRL asserted to DMCS asserted DMCS pulse width WRH and WRL de-asserted to DMCS de-asserted address valid to WRH and WRL asserted WRH and WRL pulse width address valid to data valid data valid to WRH and WRL de-asserted WRH and WRL de-asserted to address undefined data hold time after WRH and WRL de-asserted note 1 164.7 - 65.7 - 63.7 64.7 67.7 -9.0 2.0 0 ns ns ns ns ns ns ns ns ns ns
GPS IF input timing; see Fig.20 tFVSH tSHFV tW(T1S) TT1S Notes 1. For default DCMS operation. 2. The 1 s pulse output is only valid when at least one channel is locked. Table 4 Explanation of symbol characters in Chapter "AC characteristics" SYMBOL CHARACTER A C D E I P Q R W H L U V Z DESCRIPTION address clock input data DMCS strobe instruction (program memory) PCMS strobe output data RD WRH or WRL strobes logic high logic low undefined valid high impedance or pull-up IF set-up time before rising edge of SCLK IF hold time after rising edge of SCLK - 0 - note 2 - 10 - - - - - ns ns s s
1 second pulse output; see Fig.21 T1S pulse width T1S pulse period 1.0 1.0
1999 Jun 04
31
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
t CLCH 4.5 V XTAL1 0.45 V t CLKL
t CHCL
3.5 V 0.9 V t CLKH
MHB474
Fig.15 External XTAL1 clock drive.
handbook, full pagewidth
tAVAU 2.4 V 2.4 V 0.4 V t W(PMCS) th 2.4 V
A19 to A1 0.4 V
PMCS 0.4 V tAVPL t PLIV 2.4 V D15 to D0 0.4 V
MHB475
0.4 V t su(l) t h(l)
tAVIV
tPXIZ
Fig.16 External program memory read cycle (non-burst).
1999 Jun 04
32
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
tAVAU 2.4 V
A19 to A1 0.4 V t IVAU
PMCS tAUIU 2.4 V D15 to D0 0.4 V
MHB476
tAVIV
Fig.17 External program memory read cycle (burst).
handbook, full pagewidth
tAVAU 2.4 V 2.4 V 0.4 V t RLEL t W(DMCS) 2.4 V
A19 to A1 0.4 V
DMCS 0.4 V tAVRL RD 0.4 V t RLDV 2.4 V D15 to D0 0.4 V
MHB477
t W(RD)
t RHEH 2.4 V
t su(D)
t h(D)
DATA IN
tAVDV Default DMCS operation.
t RHDZ
Fig.18 External data memory read cycle.
1999 Jun 04
33
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
tAVAU 2.4 V 2.4 V 0.4 V t WLDL t W(DMCS) 2.4 V
A19 to A1 0.4 V
DMCS 0.4 V tAVWL WRH or WRL 0.4 V t QVWL 2.4 V D15 to D0 0.4 V
MHB478
t WLWH 2.4 V
t WHAU
t WHDH
DATA OUT
tAVQV Default DMCS operation.
t h(D)
Fig.19 External data memory write cycle.
handbook, full pagewidth
t FVSH
t SHFV 2.4 V
SCLK
2.4 V IF1, IF2 0.4 V
MHB479
Fig.20 IF input timing.
1999 Jun 04
34
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
TT1S t W(T1S) 2.4 V
T1S 0.4 V 0.4 V
MHB480
Signal may be inverted under firmware control.
Fig.21 T1S output pulse timing.
12 DEFAULT APPLICATION AND DEMONSTRATION BOARD
handbook, full pagewidth
VRTC VBB BATT_ON BATT_OFF
VRTC VBB BATT_ON BATT_OFF
RCLK SCLK SIGN RFDATA RFCLK RFLE
RCLK SCLK SIGN RFDATA RFCLK RFLE RF FRONT-END
MHB289
POWER SUPPLY
DIGITAL PROCESSOR
Fig.22 Overall schematic.
1999 Jun 04
35
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
VCC R207 470 U206 ZM33064 VCC VCC 2 1 GND GND GND TP216 C207 GND 10 pF TP229 C208 GND 10 pF C205 GND 27 pF Y202 32.678 kHz R201 0 TP230 VCC TP207 R202 10 M Y201 30 MHz R203 180 TP211 TP210 TP209 TP208 VCC TP214 R204 1 M TP213 TP212 TP217 PWRFAIL PWRDN TP215 XTAL1 XTAL2 XTAL3 XTAL4 TxD0 RxD0 TxD1 RxD1 TP4 n.c. n.c. n.c. TEST1 TEST2 JP202 GND 1 2 3 4 5 6 7 8 9 10 HEADER 10 VCC TP2 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO7 GPIO6 GPIO5 74 52 41 14 15 76 75 83 84 81 82 4 8 9 97 99 100 42 96 95 94 88 87 5 6 7 73 47 46 45 40 39 36 35 34 33 32 29 28 27 24 23 22 21 20 19 18 11 10 70 69 68 67 64 63 62 59 58 57 56 55 54 53 49 48 89 90 91 16 25 37 51 61 86 12 30 66 72 80 44 TP1 PMCS DMCS RD WRL WRH A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RFDAT RFCLK RFLE VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) VCC(P) TP222 TP223 TP224 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 GND TP218 TP225 TP219 TP220 TP221 C209 10 F (6.3 V) 3 OUT VCC 2 1 GND R206 10 k R205 10 k U204 D201 BAS16 U207 ZM33164 3 OUT VCC VCC
C206 GND 27 pF
JP201 JMP3
GND
SAA1575HL
TP201 TP202 TP203 VCC T1S_OUT BATT_ON BATT_OFF SIGN
RCLK SCLK IF1 IF2 TP3
98 1 93 92 3
RCLK SCLK SIGN BATT_ON BATT_OFF
RCLK SCLK SIGN BATT_ON BATT_OFF
TP204 TP205 TP206 VCC
T1S PWRB
2 77
PWRM 78 RSTIME 43 VSS 13 VSS 17 VSS 26 VSS 31 VSS 38 VSS 50 VSS 60 VSS 65 VSS 71 VSS 79 VSS 85
VCC(core) VDD1 VCC(core) VDD2 VCC(core) VDD3 VCC(R) VCC(B) VRTC1 VBB1
GND
VDD1
VDD2
VDD3
VBB1
VRTC1
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC
C210 33 nF
C211 33 nF
C212 33 nF
C213 33 nF
C214 33 nF
C215 33 nF
C216 33 nF
C217 33 nF
C218 33 nF
C219 33 nF
C220 33 nF
C221 33 nF
C222 33 nF
C223 33 nF
C224 33 nF
MHB290
GND
Fig.23 Baseband circuitry (continued in Fig.24).
1999 Jun 04
36
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
J201 5 9 4 8 3 7 2 6 1 DB9
C201 100 nF (50 V)
C202 U201 100 nF (50 V) C1+ 12 C1- 14 C2+ 15 C2- 16 T1OUT 2 T2OUT 3 T3OUT 1 T4OUT 28 /R1IN /R2IN /R3IN /R4IN /R5IN 9 4 27 23 18 V+ V- C203 13 17 100 nF (50 V) C204 /T1IN /T2IN /T3IN /T4IN R1OUT R2OUT R3OUT R4OUT R5OUT EN /SHDN TXD0 TXD1 100 nF (50 V) GND VCC RXD0 RXD1 VCC
7 6 20 21 8 5 26 22 19 24 25
J202 5 9 4 8 3 7 2 6 1 DB9 GND VCC
U202 VCC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /DMCS /RD /WRH A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /CE /OE /WE 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
MAX213EAI
RFD
R224 220
RFDATA RFDATA R210 open TP226
28 14
VBB GND
RFC
R223 220
RFCLK RFCLK R209 open TP227
M5M5256BVP
U203 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 /DMCS /RD /WRL C225 47 F (6.3 V) GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 /CE /OE /WE 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 11 12 13 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
RFL
R222 220
RFLE RFLE R208 open TP228
GND
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VDD1 VDD2 VDD3 R213 1 R212 1 R211 1 VDD VRTC R216 1 VCC
28 14
VBB GND
M5M5256BVP
U205 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC /PMCS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 /CE /OE 24 25 26 27 28 29 30 31 32 35 36 37 38 39 40 41 42 44 3 22 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 12 34 2 43 27C202 GND
MHB291
C226 47 F (6.3 V) GND
VRTC1 VBB1
VBB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D11 D12 D13 D14 D15 D16 GND VPP /PGM VCC
Fig.24 Baseband circuitry (continued from Fig.23).
1999 Jun 04
37
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
VRF handbook, full pagewidth
VRF
L306 180 nH R322 12 k M1BIASP
L307 180 nH
R324 open
C345 1 F (16 V) AGND
C308 open
L308 27 H R323
L309 open
R304 0 C343 4700 pF
AGND
2.21 k M2BIASP M2BIASN VRF R317 10 k VRF X301 TCO-987Q R326 10 k 7 R327 10 k 1 4 6 8 5 C344 10 nF (50 V) AGND R320 2.21 k R321 2.21 k R318 10 k AGND AGND AGND C342 4700 pF R314 2.7 k R315 2.7 k C338 L305 6.8 nH AGND REFIN P39GND COMP P12GND TANK DATA CLOCK STROBE SIGN R313 C348 R312 3.9 k AGND C336 10 pF C337 33 nF SCLK BFCP LIMINP LIMINN BFCN VCCA(LNA1) VCCA(LNA2) VCCA(PLL) VCCA(LIM) 2 VRF VCCA
M1BIASN
+ -
1 8 6 45
U302 MAX903ESA 7 RCLK
3
AGND DGND
8 39 40 12 10 32 7 23 34 37 30 29 28 27 43 1 36 31
C341 3.9 nF R319 20 k
C340 150 pF
AGND
3 RFDATA RFCLK
15 pF
D301 SMV1233-004
2
1 AGND
RFLE SIGN SCLK 6.8 k
R316 10 k AGND
C339 4.7 pF AGND
UAA1570HL
VCC C333 33 nF
VRF C346 33 nF
C335 33 nF 33 nF C334 33 nF C347
AGND
open C332 C330 33 nF 33 nF C331 33 nF C329 33 nF DGND AGND R310 18 R311 18 VRF R309 VDDD VCCD open R325
MHB292
VCCA(MX2) 19 VCCA(MX1P) P41GND VCCA(VCO) VDDD 16 41 9 33
1
Fig.25 RF front-end circuit (continued in Fig.26).
1999 Jun 04
38
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
L = 900 mils W = 8.8 mils R303 VRF 9 R307 9 C328 33 nF (50 V) AGND C327 10 pF (50 V) AGND C325 L = 315 mils (8.1 mm) W = 6 mils 100 C324 1.5 pF AGND 27 pF L = 367 mils (9.3 mm) W = 33 mils 50 C326 0.56 pF AGND AGND J301 SMA-F L = 1020 mils W = 8.8 mils
L = 355 mils (9 mm) W = 6 mils 100 I/O C321 0.27 pF 45 48 3 6 14 17 18 21 22 24 25 LNA1IN LNA1OUT LNA2IN LNA2OUT MX1IN IF1P IF1N IF2INN IF2INP IF2P IF2N C315 C317 8.2 pF L303 330 nH C316 M1BIASN 6.8 pF C314 36 pF C318 8.2 pF C320 1.2 pF AGND C306 0.47 pF AGND L = 386 mils (10 mm) W = 6 mils 100 L = 412 mils (10.5 mm) W = 6 mils 100 L = 217 mils (5.5 mm) W = 33 mils 50 I/O AGND AGND L = 286 mils (7.3 mm) W = 6 mils 100 C307 open 2
BPF301 MF1012S-1 5 1 3 4 6 I/O C323 2.2 pF AGND
AGND
BPF302 MF1012S-1 2 1 3 4 6 5 I/O C322 2.2 pF AGND
AGND
UAA1570HL
44 46 47 5 4 2 42 38 26 20 13 15 11 35 LNA1GND1 BIASGND1 LNA1GND2 LNA2GND2 BIASGND2 LNA2GND1 P42GND PLLGND LIMGND MX2GND MXPGND MX1GND M2BIASP VCOGND DGND M2BIASN 47 pF C301 82 pF C304 open C309 18 pF L301 22 H R301 0 47 pF L302 22 H C310 68 pF 1000 pF R305 820 C312 LIMINN 1000 pF R302 0 AGND
MHB293
M1BIASP
6.8 pF C313 36 pF
L304 330 nH
C319 39 pF
R306 909
C305 open AGND
C302
C303
C311 LIMINP
DGND AGND
Fig.26 RF front-end circuit (continued from Fig.25).
1999 Jun 04
39
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
PL101 JMP3
D101 LL4007 U101 IN ADJ 3 2 1 LM317T(3) OUT R118 270 D102 LL4007 C102 1 nF C101 1 nF C107 1 F (20 V) GND C109 10 F (10 V) GND R119 820 GND GND R101 1 VCC TP101 VCC
C108 22 F (5 V)
GND
GND
GND
D103 LL4007 U102 IN ADJ 3 2 1 LM317T(3) OUT R120 240 D104 LL4007 C104 1 nF R102 1 VRF VBAT R117 1 k B101 3V 170 mAh GND TP102 VRF
C103 1 nF
C115 1 F (20 V)
C116 10 F (10 V)
JP101 R121 390 1 2 R122 3 V/5 V 330
C110 22 F (5 V)
VCC VCC R111 1 M R113 47 k R109 470 R110 BATT_OFF 1 M C112 470 nF R114 GND GND GND 47 k V101 BC848 VDD V104 BC858 V102 BC848 R112 1 M V103 BC858
VBAT V105 BC858 C114 22 F (6.3 V) GND VBAT V106 BC858 C113 22 F (6.3 V) GND R116 10 M VRTC R115 BATT_ON 10 M VBB
U103 LP2951CM VCC IN SD FB 8 3 7 4 C105 100 nF 1 5 2 6 GND R108 12 k GND GND GND GND GND OUT ERR SNSE VTAP R106 18 k C106 100 nF
TP103 VDD(IN) R103 1 VDD
C111 10 F (6.3 V)
GND
MHB294
Fig.27 Power supply circuitry.
1999 Jun 04
40
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
The GPS system application demonstration board consists of 6 layers with a total final thickness of 1.5 mm. The PCB material is FR4.
handbook, full pagewidth
U101 + R118 R119 C102 R101 1 C109 VDD IN R103 C107 C101 VCC IN
3 V/170 mAh
RS232 #1 C223
PL101
GPS DEMO BOARD Version 1.3
U205
U102 C116
C115 C103 R120 R121 R102 RFDATA RFCLK RFLE R208 R222 R209 R223 R210 R224
R216 C220 R211 C213
VRF IN X301 R326
+ JP101 R122 C327 R303 C328 R307
C212 C214
SIGN DAC RCLK SCLK T1S_OUT C210
BATT_ON RXD0 U204
DMCS PWRFAIL
BATT_OFF U201 RXD1 TXD1 TXD0
RS232 #0 R205
R327
R213 R212
C215 C324 C325 C341 U301 R319 C216 C329 C311 R302 L302 R305 R301 C310 C303 R325 1 R309 JP202 C211 C217 PMCS
C219 C213 WRH WRL RD PWRDN C209
C326
* R314
C334 C320 L305
C306 C338 R316 BPF302
*
D301
R306
C312 C301 C319 C302 R310 L304 C317 C314
L301 C309
PTEST
R206 U206 GND/VCC 1
R311 C322 C318 C305 L303
U207
MHB295
Fig.28 Demonstration board top layer plus components (real size 88.9 mm x 88.9 mm).
1999 Jun 04
41
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
MHB296
Fig.29 Demonstration board 2nd layer.
1999 Jun 04
42
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
MHB297
Fig.30 Demonstration board 3rd layer.
1999 Jun 04
43
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
MHB298
Fig.31 Demonstration board 4th layer.
1999 Jun 04
44
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
MHB299
Fig.32 Demonstration board 5th layer.
1999 Jun 04
45
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
handbook, full pagewidth
U101 + R118 R119 C102 R101 1 C109 VDD IN R103 C107 C101 VCC IN
3 V/170 mAh
RS232 #1 C223
PL101
GPS DEMO BOARD Version 1.3
U205
U102 C116
C115 C103 R120 R121 R102 RFDATA RFCLK RFLE R208 R222 R209 R223 R210 R224
R216 C220 R211 C213
VRF IN X301 R326
+ JP101 R122 C327 R303 C328 R307
C212 C214
SIGN DAC RCLK SCLK T1S_OUT C210
BATT_ON RXD0 U204
DMCS PWRFAIL
BATT_OFF U201 RXD1 TXD1 TXD0
RS232 #0 R205
R327
R213 R212
C215 C324 C325 C341 U301 R319 C216 C329 C311 R302 L302 R305 R301 C310 C303 R325 1 R309 JP202 C211 C217 PMCS
C219 C213 WRH WRL RD PWRDN C209
C326
* R314
C334 C320 L305
C306 C338 R316 BPF302
*
D301
R306
C312 C301 C319 C302 R310 L304 C317 C314
L301 C309
PTEST
R206 U206 GND/VCC 1
R311 C322 C318 C305 L303
U207
MHB300
Fig.33 Demonstration board bottom layer plus components.
1999 Jun 04
46
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
Table 5 Component list for GPS demonstration board
SAA1575HL
COMPONENT CHARACTERISTICS COMPONENT B101 C101 to C104, C311 and C312 C105, C106, C201 to C204 C107 and C115 C108 and C110 C109 and C116 C111 and C209 C112 C113 and C114 C205, C206 and C325 C207, C208, C327 and C348 C210 to C224, C328 to C337 and C346 C225 and C226 C301 C302 and C303 C304, C305, C307, C308 and C347 C306 C309 C310 C313 and C314 C315 and C316 C317 and C318 C319 C320 C321 C322 and C323 C324 C326 C338 C339 C340 C341 C342 and C343 C344 C345 D101 to D104 D201 TYPE VALUE Lithium battery ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor tantalum capacitor tantalum capacitor ceramic capacitor tantalum capacitor ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor ceramic capacitor ceramic capacitor - ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor ceramic capacitor tantalum capacitor LL4007 diode, equivalent to 1N4007 SMD diode BAS 16 3 V/170 mAh 1 nF/50 V 100 nF/50 V 1 F/63 V 22 F/16 V 10 F/16 V 10 F/6.3 V 470 nF/63 V 22 F/6.3 V 27 pF/50 V 10 pF/50 V 33 nF/63 V 47 F/6.3 V 82 pF/50 V 47 pF/50 V not loaded 0.47 pF/50 V 18 pF/50 V 68 pF/50 V 36 pF/50 V 6.8 pF/50 V 8.2 pF/50 V 39 pF/50 V 1.2 pF/50 V 0.27 pF/50 V 2.2 pF/50 V 1.5 pF/50 V 0.56 pF/50 V 15 pF/50 V 4.7 pF/50 V 150 pF/50 V 3.9 nF/50 V 4.7 nF/50 V 10 nF/50 V 1 F/16 V - - TOLERANCE - 10% 20% 20% 20% 20% 20% 20% 20% 5% 5% 10% 20% 5% 5% - 0.1 pF 5% 5% 5% 0.25 pF 0.25 pF 5% 0.25 pF 0.1 pF 0.25 pF 0.25 pF 0.1 pF 5% 0.25 pF 5% 10% 5% 10% 20% - - PACKAGE CR1/3 603 603 1210 - - - 1206 - 603 603 603 - 603 603 - 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 - - SOT23
1999 Jun 04
47
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
COMPONENT CHARACTERISTICS COMPONENT D301 L301 and L302 L303 and L304 L305 L306 and L307 L308 L309 R101, R102, R103, R211, R212, R213, R216 and R325 R106 R108 and R322 R109 and R207 R110, R111, R112 and R204 R113 and R114 R115, R116 and R202 R117 R118 R119 and R305 R120 R121 R122 R201, R301, R302 and R304 R203 R205, R206, R316, R317, R318, R326 and R327 R208, R209, R210, R309 and R324 R222 to R224 R303 and R307 R306 R310 and R311 R312 R313 R314 and R315 R319 R320, R321 and R323 U101 and U102(1) U103 TYPE VALUE Alpha SMV1204-133 varactor SMD inductor SMD inductor SMD inductor SMD inductor SMD inductor - SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor - SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor SMD resistor LM317T voltage regulator LP2951CM voltage regulator (National) - 22 H 330 nH 6.8 nH 180 nH 27 H not loaded 1 18 k 12 k 470 1 M 47 k 10 M 1 k 270 820 240 390 330 0 180 10 k not loaded 220 9.1 910 18 3.9 k 6.8 k 2.7 k 20 k 2.2 k - - TOLERANCE - 5% 5% 5% 5% 5% - 5% 5% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% 1% - 5% 1% - 5% 5% 1% 1% 1% 1% 1% 5% 1% - - PACKAGE SOT23 1008 1008 603 1008 1008 - 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 - 603 603 603 603 603 603 603 603 603 TO220 SO8
1999 Jun 04
48
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
SAA1575HL
COMPONENT CHARACTERISTICS COMPONENT U201 U202 and U203 TYPE VALUE MAX213EAIRS2312 transceiver (Maxim) SRAM M5M5256BFP-70LL 32k x 8 (Mitsubishi) 27C202 EPROM ZM33064 power monitor ZM33164 power monitor MAX903ESA comparator (Maxim) BC848 or BC847C NPN transistor BC858 PNP transistor TCXO TCO-987Q 30 MHz crystal, 16 pF load capacitance SMD crystal MF1012S-1 saw filter - - TOLERANCE - - PACKAGE SSOP28 SO28
U205 U206 U207 U302 V101 and V102 V103 to V106 X301 Y201 Y202 BPF301 and BPF302 Note
- - - - - - - - 32.768 kHz -
- - - - - - - - 30 ppm -
PLCC44 - - SO8 SOT23 SOT23 - - - -
1. With heat sink depending on input voltage.
1999 Jun 04
49
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
13 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA1575HL
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-04
1999 Jun 04
50
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA1575HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA1575HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Jun 04
52
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
NOTES
SAA1575HL
1999 Jun 04
53
Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
NOTES
SAA1575HL
1999 Jun 04
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Philips Semiconductors
Product specification
Global Positioning System (GPS) baseband processor
NOTES
SAA1575HL
1999 Jun 04
55
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 65
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
285002/02/pp56
Date of release: 1999 Jun 04
Document order number:
9397 750 06055

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